Xilinx Vivado Zynq Custom Designed with Verilog RTL:
- Various Arm-A9 AXI Interface Blocks (100Mhz)
- 16 frequency Counters (250Mhz max)
- 128 pin IO cross point switch *(100Mh)
- 128-bit wide pattern match stream (100Mhz) (AXI + AXIS)
- 128-bit wide IO Control/Data FIFO (100Mhz) (AXIS)
- 128-bit data Packet to data stream Timing Generator Controllers
- Test Data Packet processor (AXI DMA Scatter Gather Packets)
- Error packet Stream generation (AXIS => DDR)
- Error packet Dual Port Memory Controller
- ADC/DAC sample data packet timing and control
- Control Packet Sequencer & Controller (AXI)
- Real-time PWM Temperature Controller (ramp synchronized to test packets)
- Real-time Power Supply Voltage Controller (synchronized with test packets)
- Generic JTAG Master (any chip)
- Generic Customizable SPI Hardware (AXI)
- Generic I2C Packet generator (AXI)